1. Field of the Invention
The present invention relates to an improvement of a bit line structure of a dynamic type semiconductor memory device having a so-called folded bit line structure in which two adjacent bit lines form a pair and an operation of writing/reading data which are complementary with each other is performed through the pair of bit lines.
2. Description of the Prior Art
FIG. 1 shows a whole structure of a typical semiconductor memory device which is used presently.
Referring to FIG. 1, the semiconductor memory device comprises a memory cell array 100 formed of a plurality of memory cells (not shown) arranged in a matrix comprising rows and columns, an address buffer 101 outputting internal row address signals Ao to An and internal column address signals Bo to Bm on receipt of an address signal Ext. ADD externally provided, a row decoder 102 selecting a corresponding word line in the memory cell array 100 in response to the internal row address signals Ao to An received from the address buffer 101, a(n) (I/O+sense amplifier) 104 circuit comprising sense amplifiers each detecting and amplifying a signal appearing on each bit line after the selection of a word line and an I/O portion for providing information detected and amplified by a sense amplifier to an output buffer 103, a column decoder 105 selecting one column of the memory cell array 100 and transferring an information signal on the selected column to the output buffer 103 through the I/O portion of the (I/O+sense amplifier) circuit 104 in response to the internal column address signals Bo to Bm provided from the address buffer 101, and the output buffer 103 receiving an information signal from the column selected by the column decoder 105 through the I/O portion of the (I/O+sense amplifier) circuit 104 and outputting the same.
In addition, only the main portion of a data reading system is shown in FIG. 1.
FIG. 2 is an enlarged view of the portion surrounded by a dashed line in FIG. 1, showing a structure of a bit line portion of a conventional dynamic type semiconductor memory device. One word line WL and three pairs of bit lines BL0 and BL0, BL1 and BL1, and BL2 and BL2, are respectively shown in FIG. 2.
A pair of bit lines BL0 and BL0 is provided with a sense amplifier SA0 for detecting and amplifying a potential difference between the bit lines BL0 and BL0, and with column gates T0 and T0' which are selectively turned on in response to the decoder address signal from a column decoder CD and connects the bit lines BL0 and BL0 with respective data lines y0 and y0.
Similarly, each of bit line pairs BL1 and BL1 and BL2 and BL2 is provided with sense amplifiers SA1 and SA2 and column gates T1 and T1' and T2 and T2', respectively.
Each of the bit line pairs constitutes a so-called folded bit line structure. Therefore, a memory cell MC is disposed at an intersection point of one word line and either bit line of a pair of bit lines. Referring to a structure in FIG. 2, the case is shown in which the memory cells MC are disposed at each of the intersection points of the word line WL and the bit lines BL0, BL1 and BL2. Each memory cell comprises a capacitor C storing information in the form of electric charges and a transfer gate Tr connecting the capacitor C to the corresponding bit line in response to the potential of the word line.
The bit lines BL0 and BL0 are provided with the column selecting gates T0 and T0' which become conductive selectively in response to the column decoder CD output and connect the bit lines BL0 and BL0 to the data lines y0 and y0, respectively.
Similarly, the bit lines BL1 and BL1 are provided with column selecting gates T1 and T1' and bit lines BL2 and BL2 are provided with column selecting gates T2 and T2', respectively.
In the above structure, the column decoder CD is equivalent to the column decoder 105 shown in FIG. 1.
In a bit line structure as mentioned above, a pair of bit lines is selected by the column decoder CD output (that is, column decoder signal) and connected to the data lines y0 and y0.
Each bit line has a parasitic capacitance C0. A coupling capacitance C2 exists between the bit lines constituting a pair of bit lines and a coupling capacitance C1 exists between the bit lines of adjacent bit line pairs. For example, the bit line BL1 has the parasitic capacitance C0 associated with itself and the coupling capacitances C2 and C1 between itself and adjacent bit lines BL1 and BL0, respectively. Referring to FIGS. 1 and 2. an operation of reading data is briefly described.
On entering an active cycle of the memory device, the external address signal Ext. ADD is received by the row address buffer 101 and the internal row address signals Ao to An are generated and provided to the row decoder 102. The row decoder 102 decodes the received internal row address signals Ao to An and selects one word line. As a result, the potential of the selected word line rises and then information stored in the memory cells connected to the selected word line is read out onto each corresponding bit line. In FIG. 2, let it be assumed that the word line WL is selected and information is read out onto each of bit lines BL0, BL1 and BL2. At this time, a signal voltage to be read out, that is, a potential difference between a pair of bit lines is determined to be a read voltage .DELTA.Vo+coupling noise voltage .DELTA.Vc.
The read voltage .DELTA.Vo is a voltage value which is determined by the ratio C/C.sub.B of a capacitance C of the memory cell capacitor to a bit line capacitance C.sub.B (C.sub.B =C0+C1+C2). The coupling noise voltage .DELTA.Vc is the noise voltage which is received from the adjacent bit line through the coupling capacitances C1 and C2 and has a component proportional to C1/C.sub.B (i.e., a noise component from a bit line of the adjacent bit line pairs) and a component proportional to C2/C.sub.B (i.e., a capacitance coupling noise component from the paired bit line). The coupling noise .DELTA.Vc is the noise component derived from capacitance coupling, which becomes either positive or negative in response to a signal level ("H" or "L") on the bit line of the adjacent bit line pair and which operates to decrease the read voltage .DELTA.Vo in the worst case. For example, for 1M DRAM (dynamic random access memory), the ratio of C1/C.sub.B to a potential difference of a bit line pair reaches as much as 20%.
Thereafter, each of sense amplifiers SA0, SA1 . . . is activated to detect and amplify a potential difference between each pair of bit lines.
It is desirable to make the potential difference between a pair of bit lines as large as possible so that the sense amplifier can have a large sensing margin. However, with a demand for higher integration of a semiconductor memory device, space between bit lines becomes smaller and accordingly the coupling capacitance C1 between adjacent bit line pairs becomes larger and a value of C1/C.sub.B becomes larger. More specifically, the influence of a potential on the bit line of the adjacent bit line pair becomes larger and sometimes the read voltage .DELTA.Vo onto a bit line is seriously damaged so that a potential difference of a bit line pair would become smaller. In such case, a sense amplifier can not detect and amplify the potential difference of the bit line pair accurately, causing malfunction, and soft error rate is increased.